Tutorial Materials now posted. Click on the "(pdf)" below.
Thanks to all who presented and attended for making this second tutorial a
great success!
3D die-stacking integration is a new fabrication technology that is already
in use in the embedded industry, and is likely to play a major role in
future high-performance microprocessor design. However, industry may be
reluctant to accept the risk of this new technology as there are currently
no 3D processor designs, and architects may not wish to invest the effort
in designing a new microarchitecture if 3D might not be implemented in the
target process technology. The goal of this tutorial is enable the
community to pursue relevant and impactful 3D architecture research by
educating computer architects on the following topics:
- Industrial Presentations and Perspectives
- IBM Corporation (pdf)
- Intel Corporation (pdf)
- The State of 3D Research
- 3D Tools/CAD/EDA (pdf)
- 3D Computer Architecture (pdf)
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Speaker Bios
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Dr. Jian Li, IBM Corporation Jian Li is a research staff
member at the Novel System Architecture group, IBM Austin Research
Laboratory, Austin, Texas. He received his B.S. degree from Tsinghua
University (Beijing) and Ph.D. degree from Cornell University. He has
worked in the areas of architectural support for power- and
variation-aware computing, interconnection network design for
high-performance computing systems and workload-driven 3D architecture
evaluation, with a strong emphasis on entertaining his two female family
members in Austin.
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Jerry Bautista, Intel Corporation Jerry Bautista is the Director of
Technology Management for Intel's Microprocessor Research Laboratory and
is chartered with driving the transfer of the lab's research into product
development and helping to set Intel.s strategic research agenda for
future microprocessors. He co-leads the Intel Tera-scale Computing
Research program, driving technologies for highly parallel, compute
intensive applications and platforms. In addition, he leads a cross-Intel
effort to explore memory/interconnect bandwidth challenges/solutions for
future server and client platforms. Previous to joining Intel, Jerry was
the CTO of an optical device start-up and spent 13 years at Lucent
Technologies in the field of optical components and communication
systems/networks, with assignments ranging from basic research (at Murray
Hill Bell Labs) to development, operations and strategic marketing. He
received his B.S. from Stanford University and PhD from Princeton
University.
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Prof. Jason Cong, UCLA Jason Cong received his
B.S. degree in computer science from Peking University in 1985, his M.S. and
Ph.D. degrees in computer science from the University of Illinois at
Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a
professor and the chairman of the Computer Science Department of
University of California, Los Angeles. He is also a co-director of the
VLSI CAD Laboratory.
Dr. Cong's research interests include computer-aided design of VLSI
circuits and systems, design and synthesis of system-on-a-chip,
programmable systems, novel computer architectures, nano-systems, and
highly scalable algorithms. He has published over 250 research papers
and led over 30 research projects in these areas. Dr. Cong received a
number of awards and recognitions, including t the Ross J. Martin Award
for Excellence in Research from the University of Illinois at
Urbana-Champaign in 1989, the NSF Young Investigator Award in 1993, the
Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, the
ACM/SIGDA Meritorious Service Award in 1998, and the SRC Technical
Excellence Award in 2000. He also received four Best Paper Awards
selected for the 1995 IEEE Trans. on CAD, the 2005 International
Symposium on Physical Design (ISPD), the 2005 ACM Transaction on Design
Automation of Electronic Systems, and the 2008 International Symposium on
High Performance Computer Architecture (HPCA), respectively. He was
elected to an IEEE Fellow in 2000.
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Prof. Hsien-Hsin S. Lee, Georgia Tech Hsien-Hsin
Sean Lee is an Associate Professor in the School of Electrical and
Computer Engineering at the Georgia Institute of Technology at Atlanta.
He received his B.S.E.E. degree from National Tsinghua University,
Taiwan, and his M.S.E. and Ph.D. degree in computer science and
engineering from the University of Michigan at Ann Arbor. His research
interests include computer architecture, power-efficient circuits, cyber
security, 3D graphics, and 3D integrated circuits (a different kind of
3D). Prior to joining academia, he was a senior computer architect at
Intel Corporation in both product design teams (MD6) and the
microprocessor research labs (MRL). He later joined as the architecture
manager of StarCore DSP Technology Center, a joint center of Lucent/Agere
Systems and Motorola. Dr. Lee's doctoral thesis was awarded the Horace
H. Rackham School Distinguished Dissertation Award at the University of
Michigan. He has co-authored three papers that won the Best Paper Awards
in MICRO-33, CASES-04, and IBM PAC2-05 and two papers nominated for the
Best Paper Award in HPEC-2007 and FPL-2007. Dr. Lee received the
Department of Energy Early CAREER PI Award in 2005, the 2006 ECE
Outstanding Junior Faculty Member Award at Georgia Tech, and the NSF
CAREER Award in 2007. Dr. Lee holds 4 U.S. patents in the area of memory
subsystems and 3D graphics. He is a member of Tau Beta Pi, the ACM, and a
senior member of the IEEE.
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Organized by
Gabriel Loh (loh <at> cc . gatech . edu)
Yuan Xie (yuanxie <at> cse . psu . edu)
Feel free to contact either of us with any questions or for further information.
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We have posted all of the presentations from the MICRO-2006 tutorial here. Hopefully this will be of use to all of
you interested in 3D integration research.
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