CS6290 - High-Performance Computer Architecture
Spring 2007 at Korea University
2:00-3:15, Monday and Wednesday
Science Building 633 (M), 631 (W)
Prof. Gabriel Loh (email: loh AT cc - gatech - edu)
Office Hours: Monday 3:30-4:30 (Science Library 510)

TA: Koh Young Gyun (email: young AT cc - gatech - edu)
TA Office Hours: Wednesday 1-2
Policies
Notes
Homework
Messages

Update (Apr 16): Appendix D notes (part 3) posted.
Update (Apr 18): No slides today; whiteboard only.
Update (Apr 24): Please fill out the course survey here.

Note: the course survey is completely anonymous, and the professor cannot access the survey results until after final grades have been submitted. Therefore your responses to the survey cannot have any impact (positive or negative) on your grades. This feedback helps to track the effectiveness of professors, and the comments provided will help the professor improve this course and his teaching in general. Please be honest in sharing what needs improvement, what was good or bad, and any other opinions.

General Description: This is a graduate-level course on how CPUs work. We will cover microprocessor and memory system design issues for high-performance, multi-core, and embedded mobile systems. We will also cover hardware-software interaction in such systems.

Textbook: "Computer Architecture: A Quantitative Approach" Hennessy and Patterson, Morgan Kaufmann, 2006, 4th edition.

Newsgroup: Please post questions and discussion to the Usenet group git.cc.class.cs6290. Please refer to OIT Newsgroup FAQ to connect to the GT newsgroup server.

AIM: You can add "gt2007cs6290" to your AIM buddy list. I won't always be online; email and the newsgroup are the most effective means of communication outside of the classroom.

Background Please review appendices A, B and C in the textbook.

Course Policies
Collaboration, Cheating, Late Homework, etc.

Tentative Schedule:
This schedule will be adjusted to the GT and KU calendars.

  Date  Week/DayTopicsOther Notes
Jan 81/Mon What is Architecture?, Trends
Jan 101/Wed Evaluation (Performance, Power, Cost)
Jan 152/Mon Dependences and ILP
Jan 17 2/Wed Register Renaming
Jan 22 3/Mon Compiler Techniques for ILP
Jan 24 3/Wed Branch Prediction
Jan 29 4/Mon Dynamic Scheduling (Tomasulo)
Jan 31 4/Wed Dynamic Scheduling (Unified RS, Multiple Issue)
Feb 5 5/Mon Interrupts and Exceptions
Feb 7 5/Wed Case Study: Pentium-Pro
Feb 12 6/Mon Exam 1up to and including compiler techniques
Feb 19 Lunar New Year - No Class
Feb 21 7/Wed Software Speculation, Predication
Feb 26 8/Mon VLIW and EPIC
Feb 27 8/Tue Compiler Support for VLIW
Feb 28 8/Wed Caches
Mar 5 9/Mon More Caches
Mar 7 9/Wed Virtual Memory, Protection
Mar 12 10/Mon Memory Technology
Mar 14 10/Wed Exam 2up to and including Compiler support for VLIW
Mar 19 GT Spring Break - No Class
Mar 21
Mar 26 11/Mon Multi-Processing
Mar 28 11/Wed More MP
Apr 2 12/Mon SMT, SoEMT, Multi-Core
Apr 4 12/Wed Memory Consistency
Apr 7 13/Mon DSPs
Apr 11 13/Wed Embedded Benchmarks and MP's
Apr 16 14/Mon Embedded Case Studies
Apr 18 14/Wed Research Topics in Computer Architecture
Apr 23 15/Mon Review Session
Apr 25 15/Wed Exam 3up to embedded MP


Gabriel H. Loh, © 2007
Last modified 24 Apr '07
Last generated 24 Apr '07